Integrated circuits are typically defined on a semiconductor wafer using a variety of wafer fab processes. Each of the formed active circuit areas, later forming integrated circuits after dicing and packaging, are physically separated from one another on the wafer by an elongated region commonly referred to as a scribe street. These wafers are typically cut along the scribe street after circuit testing using a conventional saw process.
In addition to the active circuitry formed on the semiconductor wafer, test pads are also provided to facilitate the active testing of the formed circuitry prior to the wafer saw process. Typically, these test pads are formed in the scribe streets, and are cut away during the wafer saw process after the wafer level die test.
Referring to FIG. 1, there is shown at 10 a portion of a fabricated semiconductor wafer having a plurality of active circuit areas 12, commonly referred to as die, each being separated from one another by an elongated scribe street 14. Defined within these scribe streets 14 are a plurality of rectangular test pads 16, which test pads may be electrically connected to one or more of the adjacent die 12 to permit wafer level die testing using conventional test equipment. This test equipment, such as via electrical probes, provides signals to and analyzes signals from the test pad 16 to electrically operate and test the functionality of the respective die 12 at the wafer level. Conventionally, these test pads 16 have square profiles and are defined using conventional reticle sets.
With the improvements in silicon technology, scribe street widths are being shrunk to increase the number of chips per wafer that can be manufactured at wafer fab. Referring to FIG. 2, this reduction in scribe street width has reduced the distance from the sawing line 18 to the active circuitry 12 of the die. Accordingly, even slight propagation of cracks in the scribe street formed during the wafer saw process eventually results in damaged circuitry since the design of conventional test pads does not prevent them from extending into the active circuitry area 12, as depicted in FIG. 2. As shown at 20, the wafer saw process typically generates cracks in the scribe street which extend along an edge and from a corner of the square test pad 16 and further extend into the die 12. These cracks render the particular die 12 non-functional, thus reducing the overall yield of the die which can be fabricated from the wafers.
FIG. 3 depicts an actual wafer after wafer saw along the scribe street 18, whereby cracks 16 are generated which extend outward from the corner of the original test pads and into the active circuitry 12. As can be appreciated in FIG. 3, the cracks are irregular, some extending into the active die area 12, and others not. However, with the continued reduction in scribe street widths with the introduction of new technologies, and in an effort to maximize wafer yield, these cracks are becoming an increasing problem and a reduction in wafer yield.
It is desired that an improved wafer fab design of the test pads 16 and process which reduces the generation of cracks during wafer saw which damage active circuit areas, and increases wafer yield.